The semiconductor device having a three-dimensional structure gains much attention as an important structure avoiding various barriers that a semiconductor device having a two-dimensional structure faces, such as limitation of lithography technology, saturation tendency of operation speed caused by increase of wiring resistance and parasitic effect, high electric field effect caused by miniaturization of element dimensions and the like and maintaining improvement of integration degree by integrating semiconductor elements in a three-dimensional manner in a structure composed of semiconductor active layers laminated in multi-layers.
As for the semiconductor device having a three-dimensional structure, there are descriptions, for example, in Japanese Patent Application Laid-Open Publication No. 11-261000 (Patent Document 1) or Japanese Patent Application Laid-Open Publication No. 2002-334967 (Patent Document 2), and a manufacturing method of the semiconductor device having a three-dimensional structure by sticking together semiconductor substrates having semiconductor elements formed is disclosed. Further, in these documents, a structure in which a penetrating electrode called a vertical mutual connection body or an embedded connection electrode is formed in a groove penetrating main and rear surfaces of a desired semiconductor substrate so that the main and rear surfaces of the semiconductor substrate are conductive is disclosed.    Patent Document 1: Japanese Patent Application Laid-Open Publication No. 11-261000    Patent Document 2: Japanese Patent Application Laid-Open Publication No. 2002-334967